Syscall 2: Firmware, home

BenchChapter 3: Chains and rings

B10SAMPLE AND HOLD

The task

P0 reads a sine wave and P1 a clock. On each rising edge of the clock, sample P0.

Hold the sample on CH3 through the PWM pin P2 until the next edge.

CH1 is the sine and CH2 the clock.

The board

The chip of SAMPLE AND HOLDChip u1 with 3 ports: P0 analog in, reaching V2, CH1; P1 digital in, reaching V3, CH2; P2 pwm out, reaching R1, C1, CH3.u1CHIP SC-2P0ANALOG INV2, CH1P1DIGITAL INV3, CH2P2PWM OUTR1, C1, CH3
The chip's ports, each with its kind and the parts its signal reaches. Cyan reads, lemon writes. On a narrow screen, scroll the board sideways to see all of it.
Sources
V1 2.5 V, V2 2 V sine at 25 Hz, and V3 5 V square at 125 Hz
Resistors
R1 1 kΩ
Capacitors
C1 1 µF
Probes
CH1, CH2, and CH3

Key idea

A rising edge is a 1 read after a 0: wait for the high, then for the low.

Hints

Each hint goes a step further than the one before. Open them one at a time.

Hint 1Show

Read P0 once, right after the edge, and write it to P2 as it is.

Hint 2Show

The analog reading and the duty are both percents of the supply.

Solution

Reveal the Full SolutionThe complete program for SAMPLE AND HOLD. Open it only when you want the answer.

The reference program

The game's own solution. It passes every test and scores exactly par on every benchmark.

u1SC-2 standard

L: IN P1
JZ L
IN P0
OUT P2
H: IN P1
JNZ H
CYCLES
800
at par
ENERGY
1600
at par
NODES
1
at par
INSTRUCTIONS
6
at par

Another way: Branch

A second program that also passes, by a different road, at a cost on INSTRUCTIONS.

Waits for the high with a jump back instead of JZ.

u1SC-2 standard

L: IN P1
JNZ E
JMP L
E: IN P0
OUT P2
H: IN P1
JNZ H
CYCLES
800
at par
ENERGY
1600
at par
NODES
1
at par
INSTRUCTIONS
7
over par