70SERIAL
The task
X is a serial line that rests at 0. A 1 starts a frame: the next four bits are a value.
The bits are worth 8, 4, 2, and 1, in that order. P must receive each value.
f is an SC-2D: 10 lines, and every jump takes 3 cycles. h is a standard core.
The board
Key idea
A protocol runs in phases: the wait for a start bit is a loop on a core with cheap jumps, and the frame is straight work on the SC-2D.
Hints
Each hint goes a step further than the one before. Open them one at a time.
Hint 1Show
A protocol runs in phases: wait for a start bit, then read a frame of fixed size.
Hint 2Show
Waiting is a loop, and h's jumps are cheap. The frame is straight work, which suits f.
Hint 3Show
Neither core can read all four bits on its own. h can start the value and f can finish it.
Solution
Reveal the Full SolutionThe complete program for SERIAL. Open it only when you want the answer.
The reference program
The game's own solution. It passes every test and scores exactly par on every benchmark.
hSC-2 standard
S: IN P0
JZ S
IN P0
MOV B, A
IN P0
ADD B
ADD B
MOV B, A
IN P0
ADD B
ADD B
OUT P1
IN P0
OUT P1fSC-2D signal processor
IN P0
ADD A
MOV B, A
IN P0
ADD B
OUT P1- CYCLES
- 118
- at par
- ENERGY
- 800
- at par
- NODES
- 2
- at par
- INSTRUCTIONS
- 20
- at par
Another way: Early handoff
A second program that also passes. It beats par on CYCLES and gives some back on ENERGY and INSTRUCTIONS.
H passes the first two bits on as they come and builds the last two itself. Each frame leaves h sooner, so P is done in fewer cycles, but the extra handoff costs energy and two more instructions.
hSC-2 standard
S: IN P0
JZ S
IN P0
OUT P1
IN P0
OUT P1
IN P0
MOV B, A
IN P0
ADD B
ADD B
OUT P1fSC-2D signal processor
IN P0
ADD A
MOV B, A
IN P0
ADD B
MUL 4
MOV B, A
IN P0
ADD B
OUT P1- CYCLES
- 112
- under par
- ENERGY
- 872
- over par
- NODES
- 2
- at par
- INSTRUCTIONS
- 22
- over par