Syscall 2: Firmware, home

SignalChapter 3: Chains and rings

11SHIFT REGISTER

The task

P must receive every value from X five places late. Zeros fill the first five.

A core can hold two values at once, one in A and one in B.

The board

The board of SHIFT REGISTER3 cores: c0, c1, and c2. Inputs X; outputs P.c0SC-2 15 LINESc1SC-2 15 LINESc2SC-2 15 LINESP0P1P0P1P0P1XP
The board as the puzzle screen lays it out. Cyan pins read, lemon pins write, violet pins go both ways. On a narrow screen, scroll the board sideways to see all of it.

Key idea

A delay line: each core holds one value and passes the one before.

Hints

Each hint goes a step further than the one before. Open them one at a time.

Hint 1Show

XCH swaps A and B, so a core can send the older value and keep the newer one.

Hint 2Show

A core that holds two values delays the stream by two. Five is two plus two plus one.

Hint 3Show

NOP spends a cycle and changes nothing. A delay line moves values, so it is not needed.

Solution

Reveal the Full SolutionThe complete program for SHIFT REGISTER. Open it only when you want the answer.

The reference program

The game's own solution. It passes every test and scores exactly par on every benchmark.

c0SC-2 standard

XCH A, B
OUT P1
IN P0

c1SC-2 standard

XCH A, B
OUT P1
IN P0

c2SC-2 standard

OUT P1
IN P0
CYCLES
153
at par
ENERGY
1836
at par
NODES
3
at par
INSTRUCTIONS
8
at par